Next Gen. PCI Express Spec Doubled To 5GT s

The PCI-SIG®, the Special Interest Group responsible for PCI Express™architecture, announced today that the data rate for the next planned revisionof the PCI Express specification will be 5 Giga transfers per second. This newspecification extends the performance capability of its flagship I/Ointerconnect architecture to meet the anticipated system requirements acrosscomputer and communication industry applications. The doubling of the data ratefollows historical performance increases for I/O specifications in the industry.

The PCI-SIG board of directors considered market requirements and technicalanalysis of a range of data rates to obtain the most feasible, highestperformance, backward compatible solution within the current PCI Expressecosystem. Platform implementation cost, high-volume manufacturability, systemtopologies, validation and interoperability were the key considerations studiedby the PCI-SIG board members in the process to extend the PCI Express data rateto 5GT/s.

Many of the leading electrical experts who developed the PCI Express 1.0aspecifications have been chartered to draft the new specification. The PCI-SIGexpects to deliver the new specification in the second half of 2005 in time forproduct introductions beginning in 2007.

"The PCI-SIG continues to deliver on the promise of timely PCI Expressenhancements to meet the ever-growing bandwidth requirements of the I/Oindustry," said Tony Pierce, PCI-SIG chairman. "The board of directorsthoughtfully considered an array of technical and market data and arrived at thebest decision for the next revision of the PCI Express architecture. We plan todeliver the new 5GT/s PCI Express specification consistent with our members’expectations for 100% backward compatibility, low-cost manufacturability andworld-class compliance and interoperability."

"The new 5GT/s PCI Express specification will enable the required performanceboost for bandwidth-hungry applications such as cinema-quality graphics andmultimedia, enterprise servers and storage, and multi-gigabit networking," saidAjay Bhatt, chairman of the PCI Express steering committee, responsible formanaging the technical development and coordination of PCI Expressspecifications. "The electrical specification will introduce evolutionarymethodologies to meet the technical challenges of running at 5 Giga transfersper second while maintaining compatibility with existing system topologies andsilicon processes."